2025-09-26 –, Main auditorium (400)
GPU threads operate in SIMT/SIMD (Single Instruction Multiple Thread / Single Instruction Multiple Data) mode: They are composed of "lanes" that execute the same instruction together in lock-step manner, but operate on different data. To show the execution state to the user, a debugger would need to be aware of lanes, so that program objects (e.g. local variables, function arguments, displayed expressions, etc.) are evaluated not only in a thread and call frame context, but also the lane context. In GNU Tools Cauldron 2024, a BoF session was organized jointly by AMD and Intel, who have downstream debuggers that implement lane support. Since then the developer teams of the two vendors compiled a common document that includes their suggested extensions to GDB commands and the user interface to introduce unified lane support to GDB. This session presents their consensus and opens it up for discussion.
Baris is a technical lead at Intel working on GDB. He received his PhD and MSc from the University of Illinois at Urbana-Champaign, USA, and his BEng from Bilkent University, Turkey.
Lancelot is GDB's maintainer of the AMDGPU backbend. He also is the tech lead for ROCgdb, AMD's downstream fork of GDB.